/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_FMC_REGISTERS_H__
#define __HW_FMC_REGISTERS_H__

#include "MK70F12.h"
#include "fsl_bitband.h"

/*
 * MK70F12 FMC
 *
 * Flash Memory Controller
 *
 * Registers defined in this header file:
 * - HW_FMC_PFAPR - Flash Access Protection Register
 * - HW_FMC_PFB01CR - Flash Bank 0-1 Control Register
 * - HW_FMC_PFB23CR - Flash Bank 2-3 Control Register
 * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
 * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
 * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
 * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
 * - HW_FMC_DATAW0SnUM - Cache Data Storage (uppermost word)
 * - HW_FMC_DATAW0SnMU - Cache Data Storage (mid-upper word)
 * - HW_FMC_DATAW0SnML - Cache Data Storage (mid-lower word)
 * - HW_FMC_DATAW0SnLM - Cache Data Storage (lowermost word)
 * - HW_FMC_DATAW1SnUM - Cache Data Storage (uppermost word)
 * - HW_FMC_DATAW1SnMU - Cache Data Storage (mid-upper word)
 * - HW_FMC_DATAW1SnML - Cache Data Storage (mid-lower word)
 * - HW_FMC_DATAW1SnLM - Cache Data Storage (lowermost word)
 * - HW_FMC_DATAW2SnUM - Cache Data Storage (uppermost word)
 * - HW_FMC_DATAW2SnMU - Cache Data Storage (mid-upper word)
 * - HW_FMC_DATAW2SnML - Cache Data Storage (mid-lower word)
 * - HW_FMC_DATAW2SnLM - Cache Data Storage (lowermost word)
 * - HW_FMC_DATAW3SnUM - Cache Data Storage (uppermost word)
 * - HW_FMC_DATAW3SnMU - Cache Data Storage (mid-upper word)
 * - HW_FMC_DATAW3SnML - Cache Data Storage (mid-lower word)
 * - HW_FMC_DATAW3SnLM - Cache Data Storage (lowermost word)
 *
 * - hw_fmc_t - Struct containing all module registers.
 */

#define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */

/*******************************************************************************
 * HW_FMC_PFAPR - Flash Access Protection Register
 ******************************************************************************/

/*!
 * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
 *
 * Reset value: 0x00F8003FU
 */
typedef union _hw_fmc_pfapr
{
    uint32_t U;
    struct _hw_fmc_pfapr_bitfields
    {
        uint32_t M0AP : 2;             /*!< [1:0] Master 0 Access Protection */
        uint32_t M1AP : 2;             /*!< [3:2] Master 1 Access Protection */
        uint32_t M2AP : 2;             /*!< [5:4] Master 2 Access Protection */
        uint32_t M3AP : 2;             /*!< [7:6] Master 3 Access Protection */
        uint32_t M4AP : 2;             /*!< [9:8] Master 4 Access Protection */
        uint32_t M5AP : 2;             /*!< [11:10] Master 5 Access Protection */
        uint32_t M6AP : 2;             /*!< [13:12] Master 6 Access Protection */
        uint32_t M7AP : 2;             /*!< [15:14] Master 7 Access Protection */
        uint32_t M0PFD : 1;            /*!< [16] Master 0 Prefetch Disable */
        uint32_t M1PFD : 1;            /*!< [17] Master 1 Prefetch Disable */
        uint32_t M2PFD : 1;            /*!< [18] Master 2 Prefetch Disable */
        uint32_t M3PFD : 1;            /*!< [19] Master 3 Prefetch Disable */
        uint32_t M4PFD : 1;            /*!< [20] Master 4 Prefetch Disable */
        uint32_t M5PFD : 1;            /*!< [21] Master 5 Prefetch Disable */
        uint32_t M6PFD : 1;            /*!< [22] Master 6 Prefetch Disable */
        uint32_t M7PFD : 1;            /*!< [23] Master 7 Prefetch Disable */
        uint32_t RESERVED0 : 8;        /*!< [31:24]  */
    } B;
} hw_fmc_pfapr_t;

/*!
 * @name Constants and macros for entire FMC_PFAPR register
 */
/*@{*/
#define HW_FMC_PFAPR_ADDR(x)     ((x) + 0x0U)

#define HW_FMC_PFAPR(x)          (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x))
#define HW_FMC_PFAPR_RD(x)       (HW_FMC_PFAPR(x).U)
#define HW_FMC_PFAPR_WR(x, v)    (HW_FMC_PFAPR(x).U = (v))
#define HW_FMC_PFAPR_SET(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) |  (v)))
#define HW_FMC_PFAPR_CLR(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v)))
#define HW_FMC_PFAPR_TOG(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_PFAPR bitfields
 */

/*!
 * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M0AP    (0U)          /*!< Bit position for FMC_PFAPR_M0AP. */
#define BM_FMC_PFAPR_M0AP    (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */
#define BS_FMC_PFAPR_M0AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M0AP. */

/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
#define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP)

/*! @brief Format value for bitfield FMC_PFAPR_M0AP. */
#define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP)

/*! @brief Set the M0AP field to a new value. */
#define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M1AP    (2U)          /*!< Bit position for FMC_PFAPR_M1AP. */
#define BM_FMC_PFAPR_M1AP    (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */
#define BS_FMC_PFAPR_M1AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M1AP. */

/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
#define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP)

/*! @brief Format value for bitfield FMC_PFAPR_M1AP. */
#define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP)

/*! @brief Set the M1AP field to a new value. */
#define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M2AP    (4U)          /*!< Bit position for FMC_PFAPR_M2AP. */
#define BM_FMC_PFAPR_M2AP    (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */
#define BS_FMC_PFAPR_M2AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M2AP. */

/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
#define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP)

/*! @brief Format value for bitfield FMC_PFAPR_M2AP. */
#define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP)

/*! @brief Set the M2AP field to a new value. */
#define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M3AP    (6U)          /*!< Bit position for FMC_PFAPR_M3AP. */
#define BM_FMC_PFAPR_M3AP    (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */
#define BS_FMC_PFAPR_M3AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M3AP. */

/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
#define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP)

/*! @brief Format value for bitfield FMC_PFAPR_M3AP. */
#define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP)

/*! @brief Set the M3AP field to a new value. */
#define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M4AP    (8U)          /*!< Bit position for FMC_PFAPR_M4AP. */
#define BM_FMC_PFAPR_M4AP    (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */
#define BS_FMC_PFAPR_M4AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M4AP. */

/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
#define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP)

/*! @brief Format value for bitfield FMC_PFAPR_M4AP. */
#define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP)

/*! @brief Set the M4AP field to a new value. */
#define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M5AP    (10U)         /*!< Bit position for FMC_PFAPR_M5AP. */
#define BM_FMC_PFAPR_M5AP    (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */
#define BS_FMC_PFAPR_M5AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M5AP. */

/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
#define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP)

/*! @brief Format value for bitfield FMC_PFAPR_M5AP. */
#define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP)

/*! @brief Set the M5AP field to a new value. */
#define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master
 * - 01 - Only read accesses may be performed by this master
 * - 10 - Only write accesses may be performed by this master
 * - 11 - Both read and write accesses may be performed by this master
 */
/*@{*/
#define BP_FMC_PFAPR_M6AP    (12U)         /*!< Bit position for FMC_PFAPR_M6AP. */
#define BM_FMC_PFAPR_M6AP    (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */
#define BS_FMC_PFAPR_M6AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M6AP. */

/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
#define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP)

/*! @brief Format value for bitfield FMC_PFAPR_M6AP. */
#define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP)

/*! @brief Set the M6AP field to a new value. */
#define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
 *
 * This field controls whether read and write access to the flash are allowed
 * based on the logical master number of the requesting crossbar switch master.
 *
 * Values:
 * - 00 - No access may be performed by this master.
 * - 01 - Only read accesses may be performed by this master.
 * - 10 - Only write accesses may be performed by this master.
 * - 11 - Both read and write accesses may be performed by this master.
 */
/*@{*/
#define BP_FMC_PFAPR_M7AP    (14U)         /*!< Bit position for FMC_PFAPR_M7AP. */
#define BM_FMC_PFAPR_M7AP    (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */
#define BS_FMC_PFAPR_M7AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M7AP. */

/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
#define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP)

/*! @brief Format value for bitfield FMC_PFAPR_M7AP. */
#define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP)

/*! @brief Set the M7AP field to a new value. */
#define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M0PFD[16] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M0PFD   (16U)         /*!< Bit position for FMC_PFAPR_M0PFD. */
#define BM_FMC_PFAPR_M0PFD   (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */
#define BS_FMC_PFAPR_M0PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */

/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
#define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */
#define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD)

/*! @brief Set the M0PFD field to a new value. */
#define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M1PFD[17] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M1PFD   (17U)         /*!< Bit position for FMC_PFAPR_M1PFD. */
#define BM_FMC_PFAPR_M1PFD   (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */
#define BS_FMC_PFAPR_M1PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */

/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
#define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */
#define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD)

/*! @brief Set the M1PFD field to a new value. */
#define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M2PFD[18] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M2PFD   (18U)         /*!< Bit position for FMC_PFAPR_M2PFD. */
#define BM_FMC_PFAPR_M2PFD   (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */
#define BS_FMC_PFAPR_M2PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */

/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
#define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */
#define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD)

/*! @brief Set the M2PFD field to a new value. */
#define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M3PFD[19] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M3PFD   (19U)         /*!< Bit position for FMC_PFAPR_M3PFD. */
#define BM_FMC_PFAPR_M3PFD   (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */
#define BS_FMC_PFAPR_M3PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */

/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
#define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */
#define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD)

/*! @brief Set the M3PFD field to a new value. */
#define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M4PFD[20] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M4PFD   (20U)         /*!< Bit position for FMC_PFAPR_M4PFD. */
#define BM_FMC_PFAPR_M4PFD   (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */
#define BS_FMC_PFAPR_M4PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */

/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
#define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */
#define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD)

/*! @brief Set the M4PFD field to a new value. */
#define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M5PFD[21] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M5PFD   (21U)         /*!< Bit position for FMC_PFAPR_M5PFD. */
#define BM_FMC_PFAPR_M5PFD   (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */
#define BS_FMC_PFAPR_M5PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */

/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
#define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */
#define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD)

/*! @brief Set the M5PFD field to a new value. */
#define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M6PFD[22] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M6PFD   (22U)         /*!< Bit position for FMC_PFAPR_M6PFD. */
#define BM_FMC_PFAPR_M6PFD   (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */
#define BS_FMC_PFAPR_M6PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */

/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
#define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */
#define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD)

/*! @brief Set the M6PFD field to a new value. */
#define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v))
/*@}*/

/*!
 * @name Register FMC_PFAPR, field M7PFD[23] (RW)
 *
 * These bits control whether prefetching is enabled based on the logical number
 * of the requesting crossbar switch master. This field is further qualified by
 * the PFBnCR[BxDPE,BxIPE] bits.
 *
 * Values:
 * - 0 - Prefetching for this master is enabled.
 * - 1 - Prefetching for this master is disabled.
 */
/*@{*/
#define BP_FMC_PFAPR_M7PFD   (23U)         /*!< Bit position for FMC_PFAPR_M7PFD. */
#define BM_FMC_PFAPR_M7PFD   (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */
#define BS_FMC_PFAPR_M7PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */

/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
#define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD))

/*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */
#define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD)

/*! @brief Set the M7PFD field to a new value. */
#define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v))
/*@}*/

/*******************************************************************************
 * HW_FMC_PFB01CR - Flash Bank 0-1 Control Register
 ******************************************************************************/

/*!
 * @brief HW_FMC_PFB01CR - Flash Bank 0-1 Control Register (RW)
 *
 * Reset value: 0x3004001FU
 *
 * This register controls the operation of memory banks 0 and 1.
 */
typedef union _hw_fmc_pfb01cr
{
    uint32_t U;
    struct _hw_fmc_pfb01cr_bitfields
    {
        uint32_t B01SEBE : 1;          /*!< [0] Bank 0-1 Single Entry Buffer Enable */
        uint32_t B01IPE : 1;           /*!< [1] Bank 0-1 Instruction Prefetch Enable */
        uint32_t B01DPE : 1;           /*!< [2] Bank 0-1 Data Prefetch Enable */
        uint32_t B01ICE : 1;           /*!< [3] Bank 0-1 Instruction Cache Enable */
        uint32_t B01DCE : 1;           /*!< [4] Bank 0-1 Data Cache Enable */
        uint32_t CRC : 3;              /*!< [7:5] Cache Replacement Control */
        uint32_t RESERVED0 : 9;        /*!< [16:8]  */
        uint32_t B01MW : 2;            /*!< [18:17] Bank 0-1 Memory Width */
        uint32_t S_B_INV : 1;          /*!< [19] Invalidate Prefetch Speculation
                                        * Buffer */
        uint32_t CINV_WAY : 4;         /*!< [23:20] Cache Invalidate Way x */
        uint32_t CLCK_WAY : 4;         /*!< [27:24] Cache Lock Way x */
        uint32_t B01RWSC : 4;          /*!< [31:28] Bank 0-1 Read Wait State Control */
    } B;
} hw_fmc_pfb01cr_t;

/*!
 * @name Constants and macros for entire FMC_PFB01CR register
 */
/*@{*/
#define HW_FMC_PFB01CR_ADDR(x)   ((x) + 0x4U)

#define HW_FMC_PFB01CR(x)        (*(__IO hw_fmc_pfb01cr_t *) HW_FMC_PFB01CR_ADDR(x))
#define HW_FMC_PFB01CR_RD(x)     (HW_FMC_PFB01CR(x).U)
#define HW_FMC_PFB01CR_WR(x, v)  (HW_FMC_PFB01CR(x).U = (v))
#define HW_FMC_PFB01CR_SET(x, v) (HW_FMC_PFB01CR_WR(x, HW_FMC_PFB01CR_RD(x) |  (v)))
#define HW_FMC_PFB01CR_CLR(x, v) (HW_FMC_PFB01CR_WR(x, HW_FMC_PFB01CR_RD(x) & ~(v)))
#define HW_FMC_PFB01CR_TOG(x, v) (HW_FMC_PFB01CR_WR(x, HW_FMC_PFB01CR_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_PFB01CR bitfields
 */

/*!
 * @name Register FMC_PFB01CR, field B01SEBE[0] (RW)
 *
 * This bit controls whether the single entry page buffer is enabled in response
 * to flash read accesses. Its operation is independent from the cache of banks
 * 2-3. A high-to-low transition of this enable forces the page buffer to be
 * invalidated.
 *
 * Values:
 * - 0 - Single entry buffer is disabled.
 * - 1 - Single entry buffer is enabled.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01SEBE (0U)        /*!< Bit position for FMC_PFB01CR_B01SEBE. */
#define BM_FMC_PFB01CR_B01SEBE (0x00000001U) /*!< Bit mask for FMC_PFB01CR_B01SEBE. */
#define BS_FMC_PFB01CR_B01SEBE (1U)        /*!< Bit field size in bits for FMC_PFB01CR_B01SEBE. */

/*! @brief Read current value of the FMC_PFB01CR_B01SEBE field. */
#define BR_FMC_PFB01CR_B01SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01SEBE))

/*! @brief Format value for bitfield FMC_PFB01CR_B01SEBE. */
#define BF_FMC_PFB01CR_B01SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_B01SEBE) & BM_FMC_PFB01CR_B01SEBE)

/*! @brief Set the B01SEBE field to a new value. */
#define BW_FMC_PFB01CR_B01SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01SEBE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01IPE[1] (RW)
 *
 * This bit controls whether prefetches (or speculative accesses) are initiated
 * in response to instruction fetches.
 *
 * Values:
 * - 0 - Do not prefetch in response to instruction fetches.
 * - 1 - Enable prefetches in response to instruction fetches.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01IPE (1U)         /*!< Bit position for FMC_PFB01CR_B01IPE. */
#define BM_FMC_PFB01CR_B01IPE (0x00000002U) /*!< Bit mask for FMC_PFB01CR_B01IPE. */
#define BS_FMC_PFB01CR_B01IPE (1U)         /*!< Bit field size in bits for FMC_PFB01CR_B01IPE. */

/*! @brief Read current value of the FMC_PFB01CR_B01IPE field. */
#define BR_FMC_PFB01CR_B01IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01IPE))

/*! @brief Format value for bitfield FMC_PFB01CR_B01IPE. */
#define BF_FMC_PFB01CR_B01IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_B01IPE) & BM_FMC_PFB01CR_B01IPE)

/*! @brief Set the B01IPE field to a new value. */
#define BW_FMC_PFB01CR_B01IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01IPE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01DPE[2] (RW)
 *
 * This bit controls whether prefetches (or speculative accesses) are initiated
 * in response to data references.
 *
 * Values:
 * - 0 - Do not prefetch in response to data references.
 * - 1 - Enable prefetches in response to data references.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01DPE (2U)         /*!< Bit position for FMC_PFB01CR_B01DPE. */
#define BM_FMC_PFB01CR_B01DPE (0x00000004U) /*!< Bit mask for FMC_PFB01CR_B01DPE. */
#define BS_FMC_PFB01CR_B01DPE (1U)         /*!< Bit field size in bits for FMC_PFB01CR_B01DPE. */

/*! @brief Read current value of the FMC_PFB01CR_B01DPE field. */
#define BR_FMC_PFB01CR_B01DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01DPE))

/*! @brief Format value for bitfield FMC_PFB01CR_B01DPE. */
#define BF_FMC_PFB01CR_B01DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_B01DPE) & BM_FMC_PFB01CR_B01DPE)

/*! @brief Set the B01DPE field to a new value. */
#define BW_FMC_PFB01CR_B01DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01DPE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01ICE[3] (RW)
 *
 * This bit controls whether instruction fetches are loaded into the cache.
 *
 * Values:
 * - 0 - Do not cache instruction fetches.
 * - 1 - Cache instruction fetches.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01ICE (3U)         /*!< Bit position for FMC_PFB01CR_B01ICE. */
#define BM_FMC_PFB01CR_B01ICE (0x00000008U) /*!< Bit mask for FMC_PFB01CR_B01ICE. */
#define BS_FMC_PFB01CR_B01ICE (1U)         /*!< Bit field size in bits for FMC_PFB01CR_B01ICE. */

/*! @brief Read current value of the FMC_PFB01CR_B01ICE field. */
#define BR_FMC_PFB01CR_B01ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01ICE))

/*! @brief Format value for bitfield FMC_PFB01CR_B01ICE. */
#define BF_FMC_PFB01CR_B01ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_B01ICE) & BM_FMC_PFB01CR_B01ICE)

/*! @brief Set the B01ICE field to a new value. */
#define BW_FMC_PFB01CR_B01ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01ICE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01DCE[4] (RW)
 *
 * This bit controls whether data references are loaded into the cache.
 *
 * Values:
 * - 0 - Do not cache data references.
 * - 1 - Cache data references.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01DCE (4U)         /*!< Bit position for FMC_PFB01CR_B01DCE. */
#define BM_FMC_PFB01CR_B01DCE (0x00000010U) /*!< Bit mask for FMC_PFB01CR_B01DCE. */
#define BS_FMC_PFB01CR_B01DCE (1U)         /*!< Bit field size in bits for FMC_PFB01CR_B01DCE. */

/*! @brief Read current value of the FMC_PFB01CR_B01DCE field. */
#define BR_FMC_PFB01CR_B01DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01DCE))

/*! @brief Format value for bitfield FMC_PFB01CR_B01DCE. */
#define BF_FMC_PFB01CR_B01DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_B01DCE) & BM_FMC_PFB01CR_B01DCE)

/*! @brief Set the B01DCE field to a new value. */
#define BW_FMC_PFB01CR_B01DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_B01DCE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field CRC[7:5] (RW)
 *
 * This 3-bit field defines the replacement algorithm for accesses that are
 * cached.
 *
 * Values:
 * - 000 - LRU replacement algorithm per set across all four ways
 * - 001 - Reserved
 * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
 * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
 * - 1xx - Reserved
 */
/*@{*/
#define BP_FMC_PFB01CR_CRC   (5U)          /*!< Bit position for FMC_PFB01CR_CRC. */
#define BM_FMC_PFB01CR_CRC   (0x000000E0U) /*!< Bit mask for FMC_PFB01CR_CRC. */
#define BS_FMC_PFB01CR_CRC   (3U)          /*!< Bit field size in bits for FMC_PFB01CR_CRC. */

/*! @brief Read current value of the FMC_PFB01CR_CRC field. */
#define BR_FMC_PFB01CR_CRC(x) (HW_FMC_PFB01CR(x).B.CRC)

/*! @brief Format value for bitfield FMC_PFB01CR_CRC. */
#define BF_FMC_PFB01CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_CRC) & BM_FMC_PFB01CR_CRC)

/*! @brief Set the CRC field to a new value. */
#define BW_FMC_PFB01CR_CRC(x, v) (HW_FMC_PFB01CR_WR(x, (HW_FMC_PFB01CR_RD(x) & ~BM_FMC_PFB01CR_CRC) | BF_FMC_PFB01CR_CRC(v)))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01MW[18:17] (RO)
 *
 * This read-only field defines the width of the bank 0-1 memory.
 *
 * Values:
 * - 00 - 32 bits
 * - 01 - 64 bits
 * - 10 - 128 bits
 * - 11 - Reserved
 */
/*@{*/
#define BP_FMC_PFB01CR_B01MW (17U)         /*!< Bit position for FMC_PFB01CR_B01MW. */
#define BM_FMC_PFB01CR_B01MW (0x00060000U) /*!< Bit mask for FMC_PFB01CR_B01MW. */
#define BS_FMC_PFB01CR_B01MW (2U)          /*!< Bit field size in bits for FMC_PFB01CR_B01MW. */

/*! @brief Read current value of the FMC_PFB01CR_B01MW field. */
#define BR_FMC_PFB01CR_B01MW(x) (HW_FMC_PFB01CR(x).B.B01MW)
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field S_B_INV[19] (WORZ)
 *
 * This bit determines if the FMC's prefetch speculation buffer and the single
 * entry page buffer are to be invalidated (cleared). When this bit is written,
 * the speculation buffer and single entry buffer are immediately cleared. This bit
 * always reads as zero.
 *
 * Values:
 * - 0 - Speculation buffer and single entry buffer are not affected.
 * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
 */
/*@{*/
#define BP_FMC_PFB01CR_S_B_INV (19U)       /*!< Bit position for FMC_PFB01CR_S_B_INV. */
#define BM_FMC_PFB01CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB01CR_S_B_INV. */
#define BS_FMC_PFB01CR_S_B_INV (1U)        /*!< Bit field size in bits for FMC_PFB01CR_S_B_INV. */

/*! @brief Format value for bitfield FMC_PFB01CR_S_B_INV. */
#define BF_FMC_PFB01CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_S_B_INV) & BM_FMC_PFB01CR_S_B_INV)

/*! @brief Set the S_B_INV field to a new value. */
#define BW_FMC_PFB01CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB01CR_ADDR(x), BP_FMC_PFB01CR_S_B_INV) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field CINV_WAY[23:20] (WORZ)
 *
 * These bits determine if the given cache way is to be invalidated (cleared).
 * When a bit within this field is written, the corresponding cache way is
 * immediately invalidated: the way's tag, data, and valid contents are cleared. This
 * field always reads as zero. Cache invalidation takes precedence over locking.
 * The cache is invalidated by system reset. System software is required to
 * maintain memory coherency when any segment of the flash memory is programmed or
 * erased. Accordingly, cache invalidations must occur after a programming or erase
 * event is completed and before the new memory image is accessed. The bit setting
 * definitions are for each bit in the field.
 *
 * Values:
 * - 0 - No cache way invalidation for the corresponding cache
 * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
 *     and vld bits of ways selected
 */
/*@{*/
#define BP_FMC_PFB01CR_CINV_WAY (20U)      /*!< Bit position for FMC_PFB01CR_CINV_WAY. */
#define BM_FMC_PFB01CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB01CR_CINV_WAY. */
#define BS_FMC_PFB01CR_CINV_WAY (4U)       /*!< Bit field size in bits for FMC_PFB01CR_CINV_WAY. */

/*! @brief Format value for bitfield FMC_PFB01CR_CINV_WAY. */
#define BF_FMC_PFB01CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_CINV_WAY) & BM_FMC_PFB01CR_CINV_WAY)

/*! @brief Set the CINV_WAY field to a new value. */
#define BW_FMC_PFB01CR_CINV_WAY(x, v) (HW_FMC_PFB01CR_WR(x, (HW_FMC_PFB01CR_RD(x) & ~BM_FMC_PFB01CR_CINV_WAY) | BF_FMC_PFB01CR_CINV_WAY(v)))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field CLCK_WAY[27:24] (RW)
 *
 * These bits determine if the given cache way is locked such that its contents
 * will not be displaced by future misses. The bit setting definitions are for
 * each bit in the field.
 *
 * Values:
 * - 0 - Cache way is unlocked and may be displaced
 * - 1 - Cache way is locked and its contents are not displaced
 */
/*@{*/
#define BP_FMC_PFB01CR_CLCK_WAY (24U)      /*!< Bit position for FMC_PFB01CR_CLCK_WAY. */
#define BM_FMC_PFB01CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB01CR_CLCK_WAY. */
#define BS_FMC_PFB01CR_CLCK_WAY (4U)       /*!< Bit field size in bits for FMC_PFB01CR_CLCK_WAY. */

/*! @brief Read current value of the FMC_PFB01CR_CLCK_WAY field. */
#define BR_FMC_PFB01CR_CLCK_WAY(x) (HW_FMC_PFB01CR(x).B.CLCK_WAY)

/*! @brief Format value for bitfield FMC_PFB01CR_CLCK_WAY. */
#define BF_FMC_PFB01CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB01CR_CLCK_WAY) & BM_FMC_PFB01CR_CLCK_WAY)

/*! @brief Set the CLCK_WAY field to a new value. */
#define BW_FMC_PFB01CR_CLCK_WAY(x, v) (HW_FMC_PFB01CR_WR(x, (HW_FMC_PFB01CR_RD(x) & ~BM_FMC_PFB01CR_CLCK_WAY) | BF_FMC_PFB01CR_CLCK_WAY(v)))
/*@}*/

/*!
 * @name Register FMC_PFB01CR, field B01RWSC[31:28] (RO)
 *
 * This read-only field defines the number of wait states required to access the
 * bank 0-1 flash memory. The relationship between the read access time of the
 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
 * this value based on the ratio of the system clock speed to the flash clock
 * speed. For example, when this ratio is 4:1, the field's value is 3h.
 */
/*@{*/
#define BP_FMC_PFB01CR_B01RWSC (28U)       /*!< Bit position for FMC_PFB01CR_B01RWSC. */
#define BM_FMC_PFB01CR_B01RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB01CR_B01RWSC. */
#define BS_FMC_PFB01CR_B01RWSC (4U)        /*!< Bit field size in bits for FMC_PFB01CR_B01RWSC. */

/*! @brief Read current value of the FMC_PFB01CR_B01RWSC field. */
#define BR_FMC_PFB01CR_B01RWSC(x) (HW_FMC_PFB01CR(x).B.B01RWSC)
/*@}*/

/*******************************************************************************
 * HW_FMC_PFB23CR - Flash Bank 2-3 Control Register
 ******************************************************************************/

/*!
 * @brief HW_FMC_PFB23CR - Flash Bank 2-3 Control Register (RW)
 *
 * Reset value: 0x3004001FU
 *
 * This register has a format similar to that for PFB01CR, except it controls
 * the operation of memory banks 2-3, and the "global" cache control fields are
 * empty.
 */
typedef union _hw_fmc_pfb23cr
{
    uint32_t U;
    struct _hw_fmc_pfb23cr_bitfields
    {
        uint32_t B23SEBE : 1;          /*!< [0] Bank 2-3 Single Entry Buffer Enable */
        uint32_t B23IPE : 1;           /*!< [1] Bank 2-3 Instruction Prefetch Enable */
        uint32_t B23DPE : 1;           /*!< [2] Bank 2-3 Data Prefetch Enable */
        uint32_t B23ICE : 1;           /*!< [3] Bank 2-3 Instruction Cache Enable */
        uint32_t B23DCE : 1;           /*!< [4] Bank 2-3 Data Cache Enable */
        uint32_t RESERVED0 : 12;       /*!< [16:5]  */
        uint32_t B23MW : 2;            /*!< [18:17] Bank 2-3 Memory Width */
        uint32_t RESERVED1 : 9;        /*!< [27:19]  */
        uint32_t B23RWSC : 4;          /*!< [31:28] Bank 2-3 Read Wait State Control */
    } B;
} hw_fmc_pfb23cr_t;

/*!
 * @name Constants and macros for entire FMC_PFB23CR register
 */
/*@{*/
#define HW_FMC_PFB23CR_ADDR(x)   ((x) + 0x8U)

#define HW_FMC_PFB23CR(x)        (*(__IO hw_fmc_pfb23cr_t *) HW_FMC_PFB23CR_ADDR(x))
#define HW_FMC_PFB23CR_RD(x)     (HW_FMC_PFB23CR(x).U)
#define HW_FMC_PFB23CR_WR(x, v)  (HW_FMC_PFB23CR(x).U = (v))
#define HW_FMC_PFB23CR_SET(x, v) (HW_FMC_PFB23CR_WR(x, HW_FMC_PFB23CR_RD(x) |  (v)))
#define HW_FMC_PFB23CR_CLR(x, v) (HW_FMC_PFB23CR_WR(x, HW_FMC_PFB23CR_RD(x) & ~(v)))
#define HW_FMC_PFB23CR_TOG(x, v) (HW_FMC_PFB23CR_WR(x, HW_FMC_PFB23CR_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_PFB23CR bitfields
 */

/*!
 * @name Register FMC_PFB23CR, field B23SEBE[0] (RW)
 *
 * This bit controls whether the single entry buffer is enabled in response to
 * flash read accesses. Its operation is independent from the cache of banks 0-1.
 * A high-to-low transition of this enable forces the page buffer to be
 * invalidated.
 *
 * Values:
 * - 0 - Single entry buffer is disabled.
 * - 1 - Single entry buffer is enabled.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23SEBE (0U)        /*!< Bit position for FMC_PFB23CR_B23SEBE. */
#define BM_FMC_PFB23CR_B23SEBE (0x00000001U) /*!< Bit mask for FMC_PFB23CR_B23SEBE. */
#define BS_FMC_PFB23CR_B23SEBE (1U)        /*!< Bit field size in bits for FMC_PFB23CR_B23SEBE. */

/*! @brief Read current value of the FMC_PFB23CR_B23SEBE field. */
#define BR_FMC_PFB23CR_B23SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23SEBE))

/*! @brief Format value for bitfield FMC_PFB23CR_B23SEBE. */
#define BF_FMC_PFB23CR_B23SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB23CR_B23SEBE) & BM_FMC_PFB23CR_B23SEBE)

/*! @brief Set the B23SEBE field to a new value. */
#define BW_FMC_PFB23CR_B23SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23SEBE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23IPE[1] (RW)
 *
 * This bit controls whether prefetches (or speculative accesses) are initiated
 * in response to instruction fetches.
 *
 * Values:
 * - 0 - Do not prefetch in response to instruction fetches.
 * - 1 - Enable prefetches in response to instruction fetches.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23IPE (1U)         /*!< Bit position for FMC_PFB23CR_B23IPE. */
#define BM_FMC_PFB23CR_B23IPE (0x00000002U) /*!< Bit mask for FMC_PFB23CR_B23IPE. */
#define BS_FMC_PFB23CR_B23IPE (1U)         /*!< Bit field size in bits for FMC_PFB23CR_B23IPE. */

/*! @brief Read current value of the FMC_PFB23CR_B23IPE field. */
#define BR_FMC_PFB23CR_B23IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23IPE))

/*! @brief Format value for bitfield FMC_PFB23CR_B23IPE. */
#define BF_FMC_PFB23CR_B23IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB23CR_B23IPE) & BM_FMC_PFB23CR_B23IPE)

/*! @brief Set the B23IPE field to a new value. */
#define BW_FMC_PFB23CR_B23IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23IPE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23DPE[2] (RW)
 *
 * This bit controls whether prefetches (or speculative accesses) are initiated
 * in response to data references.
 *
 * Values:
 * - 0 - Do not prefetch in response to data references.
 * - 1 - Enable prefetches in response to data references.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23DPE (2U)         /*!< Bit position for FMC_PFB23CR_B23DPE. */
#define BM_FMC_PFB23CR_B23DPE (0x00000004U) /*!< Bit mask for FMC_PFB23CR_B23DPE. */
#define BS_FMC_PFB23CR_B23DPE (1U)         /*!< Bit field size in bits for FMC_PFB23CR_B23DPE. */

/*! @brief Read current value of the FMC_PFB23CR_B23DPE field. */
#define BR_FMC_PFB23CR_B23DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23DPE))

/*! @brief Format value for bitfield FMC_PFB23CR_B23DPE. */
#define BF_FMC_PFB23CR_B23DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB23CR_B23DPE) & BM_FMC_PFB23CR_B23DPE)

/*! @brief Set the B23DPE field to a new value. */
#define BW_FMC_PFB23CR_B23DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23DPE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23ICE[3] (RW)
 *
 * This bit controls whether instruction fetches are loaded into the cache.
 *
 * Values:
 * - 0 - Do not cache instruction fetches.
 * - 1 - Cache instruction fetches.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23ICE (3U)         /*!< Bit position for FMC_PFB23CR_B23ICE. */
#define BM_FMC_PFB23CR_B23ICE (0x00000008U) /*!< Bit mask for FMC_PFB23CR_B23ICE. */
#define BS_FMC_PFB23CR_B23ICE (1U)         /*!< Bit field size in bits for FMC_PFB23CR_B23ICE. */

/*! @brief Read current value of the FMC_PFB23CR_B23ICE field. */
#define BR_FMC_PFB23CR_B23ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23ICE))

/*! @brief Format value for bitfield FMC_PFB23CR_B23ICE. */
#define BF_FMC_PFB23CR_B23ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB23CR_B23ICE) & BM_FMC_PFB23CR_B23ICE)

/*! @brief Set the B23ICE field to a new value. */
#define BW_FMC_PFB23CR_B23ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23ICE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23DCE[4] (RW)
 *
 * This bit controls whether data references are loaded into the cache.
 *
 * Values:
 * - 0 - Do not cache data references.
 * - 1 - Cache data references.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23DCE (4U)         /*!< Bit position for FMC_PFB23CR_B23DCE. */
#define BM_FMC_PFB23CR_B23DCE (0x00000010U) /*!< Bit mask for FMC_PFB23CR_B23DCE. */
#define BS_FMC_PFB23CR_B23DCE (1U)         /*!< Bit field size in bits for FMC_PFB23CR_B23DCE. */

/*! @brief Read current value of the FMC_PFB23CR_B23DCE field. */
#define BR_FMC_PFB23CR_B23DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23DCE))

/*! @brief Format value for bitfield FMC_PFB23CR_B23DCE. */
#define BF_FMC_PFB23CR_B23DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB23CR_B23DCE) & BM_FMC_PFB23CR_B23DCE)

/*! @brief Set the B23DCE field to a new value. */
#define BW_FMC_PFB23CR_B23DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB23CR_ADDR(x), BP_FMC_PFB23CR_B23DCE) = (v))
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23MW[18:17] (RO)
 *
 * This read-only field defines the width of the bank 2-3 memory.
 *
 * Values:
 * - 00 - 32 bits
 * - 01 - 64 bits
 * - 10 - 128 bits
 * - 11 - Reserved
 */
/*@{*/
#define BP_FMC_PFB23CR_B23MW (17U)         /*!< Bit position for FMC_PFB23CR_B23MW. */
#define BM_FMC_PFB23CR_B23MW (0x00060000U) /*!< Bit mask for FMC_PFB23CR_B23MW. */
#define BS_FMC_PFB23CR_B23MW (2U)          /*!< Bit field size in bits for FMC_PFB23CR_B23MW. */

/*! @brief Read current value of the FMC_PFB23CR_B23MW field. */
#define BR_FMC_PFB23CR_B23MW(x) (HW_FMC_PFB23CR(x).B.B23MW)
/*@}*/

/*!
 * @name Register FMC_PFB23CR, field B23RWSC[31:28] (RO)
 *
 * This read-only field defines the number of wait states required to access the
 * bank 2-3 flash memory. The relationship between the read access time of the
 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
 * this value based on the ratio of the system clock speed to the flash clock
 * speed. For example, when this ratio is 4:1, the field's value is 3h.
 */
/*@{*/
#define BP_FMC_PFB23CR_B23RWSC (28U)       /*!< Bit position for FMC_PFB23CR_B23RWSC. */
#define BM_FMC_PFB23CR_B23RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB23CR_B23RWSC. */
#define BS_FMC_PFB23CR_B23RWSC (4U)        /*!< Bit field size in bits for FMC_PFB23CR_B23RWSC. */

/*! @brief Read current value of the FMC_PFB23CR_B23RWSC field. */
#define BR_FMC_PFB23CR_B23RWSC(x) (HW_FMC_PFB23CR(x).B.B23RWSC)
/*@}*/

/*******************************************************************************
 * HW_FMC_TAGVDW0Sn - Cache Tag Storage
 ******************************************************************************/

/*!
 * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
 *
 * Reset value: 0x00000000U
 *
 * The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways
 * are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the
 * way, and y denotes the set. This section represents tag/vld information for all 3
 * sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_tagvdw0sn
{
    uint32_t U;
    struct _hw_fmc_tagvdw0sn_bitfields
    {
        uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
        uint32_t RESERVED0 : 5;        /*!< [5:1]  */
        uint32_t tag : 14;             /*!< [19:6] 13-bit tag for cache entry */
        uint32_t RESERVED1 : 12;       /*!< [31:20]  */
    } B;
} hw_fmc_tagvdw0sn_t;

/*!
 * @name Constants and macros for entire FMC_TAGVDW0Sn register
 */
/*@{*/
#define HW_FMC_TAGVDW0Sn_COUNT (4U)

#define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n)))

#define HW_FMC_TAGVDW0Sn(x, n)   (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n))
#define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U)
#define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v))
#define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) |  (v)))
#define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v)))
#define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_TAGVDW0Sn bitfields
 */

/*!
 * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW0Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW0Sn_valid. */
#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */
#define BS_FMC_TAGVDW0Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */

/*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */
#define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid))

/*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */
#define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid)

/*! @brief Set the valid field to a new value. */
#define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v))
/*@}*/

/*!
 * @name Register FMC_TAGVDW0Sn, field tag[19:6] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW0Sn_tag (6U)          /*!< Bit position for FMC_TAGVDW0Sn_tag. */
#define BM_FMC_TAGVDW0Sn_tag (0x000FFFC0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */
#define BS_FMC_TAGVDW0Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */

/*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */
#define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag)

/*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */
#define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag)

/*! @brief Set the tag field to a new value. */
#define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
/*@}*/
/*******************************************************************************
 * HW_FMC_TAGVDW1Sn - Cache Tag Storage
 ******************************************************************************/

/*!
 * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
 *
 * Reset value: 0x00000000U
 *
 * The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways
 * are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the
 * way, and y denotes the set. This section represents tag/vld information for all 3
 * sets (n=0-3) in way 1.
 */
typedef union _hw_fmc_tagvdw1sn
{
    uint32_t U;
    struct _hw_fmc_tagvdw1sn_bitfields
    {
        uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
        uint32_t RESERVED0 : 5;        /*!< [5:1]  */
        uint32_t tag : 14;             /*!< [19:6] 13-bit tag for cache entry */
        uint32_t RESERVED1 : 12;       /*!< [31:20]  */
    } B;
} hw_fmc_tagvdw1sn_t;

/*!
 * @name Constants and macros for entire FMC_TAGVDW1Sn register
 */
/*@{*/
#define HW_FMC_TAGVDW1Sn_COUNT (4U)

#define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n)))

#define HW_FMC_TAGVDW1Sn(x, n)   (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n))
#define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U)
#define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v))
#define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) |  (v)))
#define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v)))
#define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_TAGVDW1Sn bitfields
 */

/*!
 * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW1Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW1Sn_valid. */
#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */
#define BS_FMC_TAGVDW1Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */

/*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */
#define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid))

/*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */
#define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid)

/*! @brief Set the valid field to a new value. */
#define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v))
/*@}*/

/*!
 * @name Register FMC_TAGVDW1Sn, field tag[19:6] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW1Sn_tag (6U)          /*!< Bit position for FMC_TAGVDW1Sn_tag. */
#define BM_FMC_TAGVDW1Sn_tag (0x000FFFC0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */
#define BS_FMC_TAGVDW1Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */

/*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */
#define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag)

/*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */
#define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag)

/*! @brief Set the tag field to a new value. */
#define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
/*@}*/
/*******************************************************************************
 * HW_FMC_TAGVDW2Sn - Cache Tag Storage
 ******************************************************************************/

/*!
 * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
 *
 * Reset value: 0x00000000U
 *
 * The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways
 * are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the
 * way, and y denotes the set. This section represents tag/vld information for all 3
 * sets (n=0-3) in way 2.
 */
typedef union _hw_fmc_tagvdw2sn
{
    uint32_t U;
    struct _hw_fmc_tagvdw2sn_bitfields
    {
        uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
        uint32_t RESERVED0 : 5;        /*!< [5:1]  */
        uint32_t tag : 14;             /*!< [19:6] 13-bit tag for cache entry */
        uint32_t RESERVED1 : 12;       /*!< [31:20]  */
    } B;
} hw_fmc_tagvdw2sn_t;

/*!
 * @name Constants and macros for entire FMC_TAGVDW2Sn register
 */
/*@{*/
#define HW_FMC_TAGVDW2Sn_COUNT (4U)

#define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n)))

#define HW_FMC_TAGVDW2Sn(x, n)   (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n))
#define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U)
#define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v))
#define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) |  (v)))
#define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v)))
#define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_TAGVDW2Sn bitfields
 */

/*!
 * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW2Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW2Sn_valid. */
#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */
#define BS_FMC_TAGVDW2Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */

/*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */
#define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid))

/*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */
#define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid)

/*! @brief Set the valid field to a new value. */
#define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v))
/*@}*/

/*!
 * @name Register FMC_TAGVDW2Sn, field tag[19:6] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW2Sn_tag (6U)          /*!< Bit position for FMC_TAGVDW2Sn_tag. */
#define BM_FMC_TAGVDW2Sn_tag (0x000FFFC0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */
#define BS_FMC_TAGVDW2Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */

/*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */
#define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag)

/*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */
#define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag)

/*! @brief Set the tag field to a new value. */
#define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
/*@}*/
/*******************************************************************************
 * HW_FMC_TAGVDW3Sn - Cache Tag Storage
 ******************************************************************************/

/*!
 * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
 *
 * Reset value: 0x00000000U
 *
 * The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways
 * are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the
 * way, and y denotes the set. This section represents tag/vld information for all 3
 * sets (n=0-3) in way 3.
 */
typedef union _hw_fmc_tagvdw3sn
{
    uint32_t U;
    struct _hw_fmc_tagvdw3sn_bitfields
    {
        uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
        uint32_t RESERVED0 : 5;        /*!< [5:1]  */
        uint32_t tag : 14;             /*!< [19:6] 13-bit tag for cache entry */
        uint32_t RESERVED1 : 12;       /*!< [31:20]  */
    } B;
} hw_fmc_tagvdw3sn_t;

/*!
 * @name Constants and macros for entire FMC_TAGVDW3Sn register
 */
/*@{*/
#define HW_FMC_TAGVDW3Sn_COUNT (4U)

#define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n)))

#define HW_FMC_TAGVDW3Sn(x, n)   (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n))
#define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U)
#define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v))
#define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) |  (v)))
#define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v)))
#define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_TAGVDW3Sn bitfields
 */

/*!
 * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW3Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW3Sn_valid. */
#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */
#define BS_FMC_TAGVDW3Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */

/*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */
#define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid))

/*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */
#define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid)

/*! @brief Set the valid field to a new value. */
#define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v))
/*@}*/

/*!
 * @name Register FMC_TAGVDW3Sn, field tag[19:6] (RW)
 */
/*@{*/
#define BP_FMC_TAGVDW3Sn_tag (6U)          /*!< Bit position for FMC_TAGVDW3Sn_tag. */
#define BM_FMC_TAGVDW3Sn_tag (0x000FFFC0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */
#define BS_FMC_TAGVDW3Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */

/*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */
#define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag)

/*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */
#define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag)

/*! @brief Set the tag field to a new value. */
#define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
/*@}*/

/*******************************************************************************
 * HW_FMC_DATAW0SnUM - Cache Data Storage (uppermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW0SnUM - Cache Data Storage (uppermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * uppermost word (bits [127:96]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw0snum
{
    uint32_t U;
    struct _hw_fmc_dataw0snum_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [127:96] of data entry */
    } B;
} hw_fmc_dataw0snum_t;

/*!
 * @name Constants and macros for entire FMC_DATAW0SnUM register
 */
/*@{*/
#define HW_FMC_DATAW0SnUM_COUNT (4U)

#define HW_FMC_DATAW0SnUM_ADDR(x, n) ((x) + 0x200U + (0x10U * (n)))

#define HW_FMC_DATAW0SnUM(x, n)  (*(__IO hw_fmc_dataw0snum_t *) HW_FMC_DATAW0SnUM_ADDR(x, n))
#define HW_FMC_DATAW0SnUM_RD(x, n) (HW_FMC_DATAW0SnUM(x, n).U)
#define HW_FMC_DATAW0SnUM_WR(x, n, v) (HW_FMC_DATAW0SnUM(x, n).U = (v))
#define HW_FMC_DATAW0SnUM_SET(x, n, v) (HW_FMC_DATAW0SnUM_WR(x, n, HW_FMC_DATAW0SnUM_RD(x, n) |  (v)))
#define HW_FMC_DATAW0SnUM_CLR(x, n, v) (HW_FMC_DATAW0SnUM_WR(x, n, HW_FMC_DATAW0SnUM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW0SnUM_TOG(x, n, v) (HW_FMC_DATAW0SnUM_WR(x, n, HW_FMC_DATAW0SnUM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW0SnUM bitfields
 */

/*!
 * @name Register FMC_DATAW0SnUM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW0SnUM_data (0U)        /*!< Bit position for FMC_DATAW0SnUM_data. */
#define BM_FMC_DATAW0SnUM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnUM_data. */
#define BS_FMC_DATAW0SnUM_data (32U)       /*!< Bit field size in bits for FMC_DATAW0SnUM_data. */

/*! @brief Read current value of the FMC_DATAW0SnUM_data field. */
#define BR_FMC_DATAW0SnUM_data(x, n) (HW_FMC_DATAW0SnUM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW0SnUM_data. */
#define BF_FMC_DATAW0SnUM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnUM_data) & BM_FMC_DATAW0SnUM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW0SnUM_data(x, n, v) (HW_FMC_DATAW0SnUM_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW0SnMU - Cache Data Storage (mid-upper word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW0SnMU - Cache Data Storage (mid-upper word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-upper word (bits [95:64]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw0snmu
{
    uint32_t U;
    struct _hw_fmc_dataw0snmu_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [95:64] of data entry */
    } B;
} hw_fmc_dataw0snmu_t;

/*!
 * @name Constants and macros for entire FMC_DATAW0SnMU register
 */
/*@{*/
#define HW_FMC_DATAW0SnMU_COUNT (4U)

#define HW_FMC_DATAW0SnMU_ADDR(x, n) ((x) + 0x204U + (0x10U * (n)))

#define HW_FMC_DATAW0SnMU(x, n)  (*(__IO hw_fmc_dataw0snmu_t *) HW_FMC_DATAW0SnMU_ADDR(x, n))
#define HW_FMC_DATAW0SnMU_RD(x, n) (HW_FMC_DATAW0SnMU(x, n).U)
#define HW_FMC_DATAW0SnMU_WR(x, n, v) (HW_FMC_DATAW0SnMU(x, n).U = (v))
#define HW_FMC_DATAW0SnMU_SET(x, n, v) (HW_FMC_DATAW0SnMU_WR(x, n, HW_FMC_DATAW0SnMU_RD(x, n) |  (v)))
#define HW_FMC_DATAW0SnMU_CLR(x, n, v) (HW_FMC_DATAW0SnMU_WR(x, n, HW_FMC_DATAW0SnMU_RD(x, n) & ~(v)))
#define HW_FMC_DATAW0SnMU_TOG(x, n, v) (HW_FMC_DATAW0SnMU_WR(x, n, HW_FMC_DATAW0SnMU_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW0SnMU bitfields
 */

/*!
 * @name Register FMC_DATAW0SnMU, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW0SnMU_data (0U)        /*!< Bit position for FMC_DATAW0SnMU_data. */
#define BM_FMC_DATAW0SnMU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnMU_data. */
#define BS_FMC_DATAW0SnMU_data (32U)       /*!< Bit field size in bits for FMC_DATAW0SnMU_data. */

/*! @brief Read current value of the FMC_DATAW0SnMU_data field. */
#define BR_FMC_DATAW0SnMU_data(x, n) (HW_FMC_DATAW0SnMU(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW0SnMU_data. */
#define BF_FMC_DATAW0SnMU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnMU_data) & BM_FMC_DATAW0SnMU_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW0SnMU_data(x, n, v) (HW_FMC_DATAW0SnMU_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW0SnML - Cache Data Storage (mid-lower word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW0SnML - Cache Data Storage (mid-lower word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-lower word (bits [63:32]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw0snml
{
    uint32_t U;
    struct _hw_fmc_dataw0snml_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
    } B;
} hw_fmc_dataw0snml_t;

/*!
 * @name Constants and macros for entire FMC_DATAW0SnML register
 */
/*@{*/
#define HW_FMC_DATAW0SnML_COUNT (4U)

#define HW_FMC_DATAW0SnML_ADDR(x, n) ((x) + 0x208U + (0x10U * (n)))

#define HW_FMC_DATAW0SnML(x, n)  (*(__IO hw_fmc_dataw0snml_t *) HW_FMC_DATAW0SnML_ADDR(x, n))
#define HW_FMC_DATAW0SnML_RD(x, n) (HW_FMC_DATAW0SnML(x, n).U)
#define HW_FMC_DATAW0SnML_WR(x, n, v) (HW_FMC_DATAW0SnML(x, n).U = (v))
#define HW_FMC_DATAW0SnML_SET(x, n, v) (HW_FMC_DATAW0SnML_WR(x, n, HW_FMC_DATAW0SnML_RD(x, n) |  (v)))
#define HW_FMC_DATAW0SnML_CLR(x, n, v) (HW_FMC_DATAW0SnML_WR(x, n, HW_FMC_DATAW0SnML_RD(x, n) & ~(v)))
#define HW_FMC_DATAW0SnML_TOG(x, n, v) (HW_FMC_DATAW0SnML_WR(x, n, HW_FMC_DATAW0SnML_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW0SnML bitfields
 */

/*!
 * @name Register FMC_DATAW0SnML, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW0SnML_data (0U)        /*!< Bit position for FMC_DATAW0SnML_data. */
#define BM_FMC_DATAW0SnML_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnML_data. */
#define BS_FMC_DATAW0SnML_data (32U)       /*!< Bit field size in bits for FMC_DATAW0SnML_data. */

/*! @brief Read current value of the FMC_DATAW0SnML_data field. */
#define BR_FMC_DATAW0SnML_data(x, n) (HW_FMC_DATAW0SnML(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW0SnML_data. */
#define BF_FMC_DATAW0SnML_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnML_data) & BM_FMC_DATAW0SnML_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW0SnML_data(x, n, v) (HW_FMC_DATAW0SnML_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW0SnLM - Cache Data Storage (lowermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW0SnLM - Cache Data Storage (lowermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * lowermost word (bits [31:0]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw0snlm
{
    uint32_t U;
    struct _hw_fmc_dataw0snlm_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
    } B;
} hw_fmc_dataw0snlm_t;

/*!
 * @name Constants and macros for entire FMC_DATAW0SnLM register
 */
/*@{*/
#define HW_FMC_DATAW0SnLM_COUNT (4U)

#define HW_FMC_DATAW0SnLM_ADDR(x, n) ((x) + 0x20CU + (0x10U * (n)))

#define HW_FMC_DATAW0SnLM(x, n)  (*(__IO hw_fmc_dataw0snlm_t *) HW_FMC_DATAW0SnLM_ADDR(x, n))
#define HW_FMC_DATAW0SnLM_RD(x, n) (HW_FMC_DATAW0SnLM(x, n).U)
#define HW_FMC_DATAW0SnLM_WR(x, n, v) (HW_FMC_DATAW0SnLM(x, n).U = (v))
#define HW_FMC_DATAW0SnLM_SET(x, n, v) (HW_FMC_DATAW0SnLM_WR(x, n, HW_FMC_DATAW0SnLM_RD(x, n) |  (v)))
#define HW_FMC_DATAW0SnLM_CLR(x, n, v) (HW_FMC_DATAW0SnLM_WR(x, n, HW_FMC_DATAW0SnLM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW0SnLM_TOG(x, n, v) (HW_FMC_DATAW0SnLM_WR(x, n, HW_FMC_DATAW0SnLM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW0SnLM bitfields
 */

/*!
 * @name Register FMC_DATAW0SnLM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW0SnLM_data (0U)        /*!< Bit position for FMC_DATAW0SnLM_data. */
#define BM_FMC_DATAW0SnLM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnLM_data. */
#define BS_FMC_DATAW0SnLM_data (32U)       /*!< Bit field size in bits for FMC_DATAW0SnLM_data. */

/*! @brief Read current value of the FMC_DATAW0SnLM_data field. */
#define BR_FMC_DATAW0SnLM_data(x, n) (HW_FMC_DATAW0SnLM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW0SnLM_data. */
#define BF_FMC_DATAW0SnLM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnLM_data) & BM_FMC_DATAW0SnLM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW0SnLM_data(x, n, v) (HW_FMC_DATAW0SnLM_WR(x, n, v))
/*@}*/

/*******************************************************************************
 * HW_FMC_DATAW1SnUM - Cache Data Storage (uppermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW1SnUM - Cache Data Storage (uppermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * uppermost word (bits [127:96]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw1snum
{
    uint32_t U;
    struct _hw_fmc_dataw1snum_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [127:96] of data entry */
    } B;
} hw_fmc_dataw1snum_t;

/*!
 * @name Constants and macros for entire FMC_DATAW1SnUM register
 */
/*@{*/
#define HW_FMC_DATAW1SnUM_COUNT (4U)

#define HW_FMC_DATAW1SnUM_ADDR(x, n) ((x) + 0x240U + (0x10U * (n)))

#define HW_FMC_DATAW1SnUM(x, n)  (*(__IO hw_fmc_dataw1snum_t *) HW_FMC_DATAW1SnUM_ADDR(x, n))
#define HW_FMC_DATAW1SnUM_RD(x, n) (HW_FMC_DATAW1SnUM(x, n).U)
#define HW_FMC_DATAW1SnUM_WR(x, n, v) (HW_FMC_DATAW1SnUM(x, n).U = (v))
#define HW_FMC_DATAW1SnUM_SET(x, n, v) (HW_FMC_DATAW1SnUM_WR(x, n, HW_FMC_DATAW1SnUM_RD(x, n) |  (v)))
#define HW_FMC_DATAW1SnUM_CLR(x, n, v) (HW_FMC_DATAW1SnUM_WR(x, n, HW_FMC_DATAW1SnUM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW1SnUM_TOG(x, n, v) (HW_FMC_DATAW1SnUM_WR(x, n, HW_FMC_DATAW1SnUM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW1SnUM bitfields
 */

/*!
 * @name Register FMC_DATAW1SnUM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW1SnUM_data (0U)        /*!< Bit position for FMC_DATAW1SnUM_data. */
#define BM_FMC_DATAW1SnUM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnUM_data. */
#define BS_FMC_DATAW1SnUM_data (32U)       /*!< Bit field size in bits for FMC_DATAW1SnUM_data. */

/*! @brief Read current value of the FMC_DATAW1SnUM_data field. */
#define BR_FMC_DATAW1SnUM_data(x, n) (HW_FMC_DATAW1SnUM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW1SnUM_data. */
#define BF_FMC_DATAW1SnUM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnUM_data) & BM_FMC_DATAW1SnUM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW1SnUM_data(x, n, v) (HW_FMC_DATAW1SnUM_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW1SnMU - Cache Data Storage (mid-upper word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW1SnMU - Cache Data Storage (mid-upper word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-upper word (bits [95:64]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw1snmu
{
    uint32_t U;
    struct _hw_fmc_dataw1snmu_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [95:64] of data entry */
    } B;
} hw_fmc_dataw1snmu_t;

/*!
 * @name Constants and macros for entire FMC_DATAW1SnMU register
 */
/*@{*/
#define HW_FMC_DATAW1SnMU_COUNT (4U)

#define HW_FMC_DATAW1SnMU_ADDR(x, n) ((x) + 0x244U + (0x10U * (n)))

#define HW_FMC_DATAW1SnMU(x, n)  (*(__IO hw_fmc_dataw1snmu_t *) HW_FMC_DATAW1SnMU_ADDR(x, n))
#define HW_FMC_DATAW1SnMU_RD(x, n) (HW_FMC_DATAW1SnMU(x, n).U)
#define HW_FMC_DATAW1SnMU_WR(x, n, v) (HW_FMC_DATAW1SnMU(x, n).U = (v))
#define HW_FMC_DATAW1SnMU_SET(x, n, v) (HW_FMC_DATAW1SnMU_WR(x, n, HW_FMC_DATAW1SnMU_RD(x, n) |  (v)))
#define HW_FMC_DATAW1SnMU_CLR(x, n, v) (HW_FMC_DATAW1SnMU_WR(x, n, HW_FMC_DATAW1SnMU_RD(x, n) & ~(v)))
#define HW_FMC_DATAW1SnMU_TOG(x, n, v) (HW_FMC_DATAW1SnMU_WR(x, n, HW_FMC_DATAW1SnMU_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW1SnMU bitfields
 */

/*!
 * @name Register FMC_DATAW1SnMU, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW1SnMU_data (0U)        /*!< Bit position for FMC_DATAW1SnMU_data. */
#define BM_FMC_DATAW1SnMU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnMU_data. */
#define BS_FMC_DATAW1SnMU_data (32U)       /*!< Bit field size in bits for FMC_DATAW1SnMU_data. */

/*! @brief Read current value of the FMC_DATAW1SnMU_data field. */
#define BR_FMC_DATAW1SnMU_data(x, n) (HW_FMC_DATAW1SnMU(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW1SnMU_data. */
#define BF_FMC_DATAW1SnMU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnMU_data) & BM_FMC_DATAW1SnMU_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW1SnMU_data(x, n, v) (HW_FMC_DATAW1SnMU_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW1SnML - Cache Data Storage (mid-lower word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW1SnML - Cache Data Storage (mid-lower word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-lower word (bits [63:32]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw1snml
{
    uint32_t U;
    struct _hw_fmc_dataw1snml_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
    } B;
} hw_fmc_dataw1snml_t;

/*!
 * @name Constants and macros for entire FMC_DATAW1SnML register
 */
/*@{*/
#define HW_FMC_DATAW1SnML_COUNT (4U)

#define HW_FMC_DATAW1SnML_ADDR(x, n) ((x) + 0x248U + (0x10U * (n)))

#define HW_FMC_DATAW1SnML(x, n)  (*(__IO hw_fmc_dataw1snml_t *) HW_FMC_DATAW1SnML_ADDR(x, n))
#define HW_FMC_DATAW1SnML_RD(x, n) (HW_FMC_DATAW1SnML(x, n).U)
#define HW_FMC_DATAW1SnML_WR(x, n, v) (HW_FMC_DATAW1SnML(x, n).U = (v))
#define HW_FMC_DATAW1SnML_SET(x, n, v) (HW_FMC_DATAW1SnML_WR(x, n, HW_FMC_DATAW1SnML_RD(x, n) |  (v)))
#define HW_FMC_DATAW1SnML_CLR(x, n, v) (HW_FMC_DATAW1SnML_WR(x, n, HW_FMC_DATAW1SnML_RD(x, n) & ~(v)))
#define HW_FMC_DATAW1SnML_TOG(x, n, v) (HW_FMC_DATAW1SnML_WR(x, n, HW_FMC_DATAW1SnML_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW1SnML bitfields
 */

/*!
 * @name Register FMC_DATAW1SnML, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW1SnML_data (0U)        /*!< Bit position for FMC_DATAW1SnML_data. */
#define BM_FMC_DATAW1SnML_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnML_data. */
#define BS_FMC_DATAW1SnML_data (32U)       /*!< Bit field size in bits for FMC_DATAW1SnML_data. */

/*! @brief Read current value of the FMC_DATAW1SnML_data field. */
#define BR_FMC_DATAW1SnML_data(x, n) (HW_FMC_DATAW1SnML(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW1SnML_data. */
#define BF_FMC_DATAW1SnML_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnML_data) & BM_FMC_DATAW1SnML_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW1SnML_data(x, n, v) (HW_FMC_DATAW1SnML_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW1SnLM - Cache Data Storage (lowermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW1SnLM - Cache Data Storage (lowermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * lowermost word (bits [31:0]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw1snlm
{
    uint32_t U;
    struct _hw_fmc_dataw1snlm_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
    } B;
} hw_fmc_dataw1snlm_t;

/*!
 * @name Constants and macros for entire FMC_DATAW1SnLM register
 */
/*@{*/
#define HW_FMC_DATAW1SnLM_COUNT (4U)

#define HW_FMC_DATAW1SnLM_ADDR(x, n) ((x) + 0x24CU + (0x10U * (n)))

#define HW_FMC_DATAW1SnLM(x, n)  (*(__IO hw_fmc_dataw1snlm_t *) HW_FMC_DATAW1SnLM_ADDR(x, n))
#define HW_FMC_DATAW1SnLM_RD(x, n) (HW_FMC_DATAW1SnLM(x, n).U)
#define HW_FMC_DATAW1SnLM_WR(x, n, v) (HW_FMC_DATAW1SnLM(x, n).U = (v))
#define HW_FMC_DATAW1SnLM_SET(x, n, v) (HW_FMC_DATAW1SnLM_WR(x, n, HW_FMC_DATAW1SnLM_RD(x, n) |  (v)))
#define HW_FMC_DATAW1SnLM_CLR(x, n, v) (HW_FMC_DATAW1SnLM_WR(x, n, HW_FMC_DATAW1SnLM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW1SnLM_TOG(x, n, v) (HW_FMC_DATAW1SnLM_WR(x, n, HW_FMC_DATAW1SnLM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW1SnLM bitfields
 */

/*!
 * @name Register FMC_DATAW1SnLM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW1SnLM_data (0U)        /*!< Bit position for FMC_DATAW1SnLM_data. */
#define BM_FMC_DATAW1SnLM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnLM_data. */
#define BS_FMC_DATAW1SnLM_data (32U)       /*!< Bit field size in bits for FMC_DATAW1SnLM_data. */

/*! @brief Read current value of the FMC_DATAW1SnLM_data field. */
#define BR_FMC_DATAW1SnLM_data(x, n) (HW_FMC_DATAW1SnLM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW1SnLM_data. */
#define BF_FMC_DATAW1SnLM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnLM_data) & BM_FMC_DATAW1SnLM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW1SnLM_data(x, n, v) (HW_FMC_DATAW1SnLM_WR(x, n, v))
/*@}*/

/*******************************************************************************
 * HW_FMC_DATAW2SnUM - Cache Data Storage (uppermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW2SnUM - Cache Data Storage (uppermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * uppermost word (bits [127:96]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw2snum
{
    uint32_t U;
    struct _hw_fmc_dataw2snum_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [127:96] of data entry */
    } B;
} hw_fmc_dataw2snum_t;

/*!
 * @name Constants and macros for entire FMC_DATAW2SnUM register
 */
/*@{*/
#define HW_FMC_DATAW2SnUM_COUNT (4U)

#define HW_FMC_DATAW2SnUM_ADDR(x, n) ((x) + 0x280U + (0x10U * (n)))

#define HW_FMC_DATAW2SnUM(x, n)  (*(__IO hw_fmc_dataw2snum_t *) HW_FMC_DATAW2SnUM_ADDR(x, n))
#define HW_FMC_DATAW2SnUM_RD(x, n) (HW_FMC_DATAW2SnUM(x, n).U)
#define HW_FMC_DATAW2SnUM_WR(x, n, v) (HW_FMC_DATAW2SnUM(x, n).U = (v))
#define HW_FMC_DATAW2SnUM_SET(x, n, v) (HW_FMC_DATAW2SnUM_WR(x, n, HW_FMC_DATAW2SnUM_RD(x, n) |  (v)))
#define HW_FMC_DATAW2SnUM_CLR(x, n, v) (HW_FMC_DATAW2SnUM_WR(x, n, HW_FMC_DATAW2SnUM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW2SnUM_TOG(x, n, v) (HW_FMC_DATAW2SnUM_WR(x, n, HW_FMC_DATAW2SnUM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW2SnUM bitfields
 */

/*!
 * @name Register FMC_DATAW2SnUM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW2SnUM_data (0U)        /*!< Bit position for FMC_DATAW2SnUM_data. */
#define BM_FMC_DATAW2SnUM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnUM_data. */
#define BS_FMC_DATAW2SnUM_data (32U)       /*!< Bit field size in bits for FMC_DATAW2SnUM_data. */

/*! @brief Read current value of the FMC_DATAW2SnUM_data field. */
#define BR_FMC_DATAW2SnUM_data(x, n) (HW_FMC_DATAW2SnUM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW2SnUM_data. */
#define BF_FMC_DATAW2SnUM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnUM_data) & BM_FMC_DATAW2SnUM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW2SnUM_data(x, n, v) (HW_FMC_DATAW2SnUM_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW2SnMU - Cache Data Storage (mid-upper word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW2SnMU - Cache Data Storage (mid-upper word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-upper word (bits [95:64]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw2snmu
{
    uint32_t U;
    struct _hw_fmc_dataw2snmu_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [95:64] of data entry */
    } B;
} hw_fmc_dataw2snmu_t;

/*!
 * @name Constants and macros for entire FMC_DATAW2SnMU register
 */
/*@{*/
#define HW_FMC_DATAW2SnMU_COUNT (4U)

#define HW_FMC_DATAW2SnMU_ADDR(x, n) ((x) + 0x284U + (0x10U * (n)))

#define HW_FMC_DATAW2SnMU(x, n)  (*(__IO hw_fmc_dataw2snmu_t *) HW_FMC_DATAW2SnMU_ADDR(x, n))
#define HW_FMC_DATAW2SnMU_RD(x, n) (HW_FMC_DATAW2SnMU(x, n).U)
#define HW_FMC_DATAW2SnMU_WR(x, n, v) (HW_FMC_DATAW2SnMU(x, n).U = (v))
#define HW_FMC_DATAW2SnMU_SET(x, n, v) (HW_FMC_DATAW2SnMU_WR(x, n, HW_FMC_DATAW2SnMU_RD(x, n) |  (v)))
#define HW_FMC_DATAW2SnMU_CLR(x, n, v) (HW_FMC_DATAW2SnMU_WR(x, n, HW_FMC_DATAW2SnMU_RD(x, n) & ~(v)))
#define HW_FMC_DATAW2SnMU_TOG(x, n, v) (HW_FMC_DATAW2SnMU_WR(x, n, HW_FMC_DATAW2SnMU_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW2SnMU bitfields
 */

/*!
 * @name Register FMC_DATAW2SnMU, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW2SnMU_data (0U)        /*!< Bit position for FMC_DATAW2SnMU_data. */
#define BM_FMC_DATAW2SnMU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnMU_data. */
#define BS_FMC_DATAW2SnMU_data (32U)       /*!< Bit field size in bits for FMC_DATAW2SnMU_data. */

/*! @brief Read current value of the FMC_DATAW2SnMU_data field. */
#define BR_FMC_DATAW2SnMU_data(x, n) (HW_FMC_DATAW2SnMU(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW2SnMU_data. */
#define BF_FMC_DATAW2SnMU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnMU_data) & BM_FMC_DATAW2SnMU_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW2SnMU_data(x, n, v) (HW_FMC_DATAW2SnMU_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW2SnML - Cache Data Storage (mid-lower word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW2SnML - Cache Data Storage (mid-lower word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-lower word (bits [63:32]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw2snml
{
    uint32_t U;
    struct _hw_fmc_dataw2snml_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
    } B;
} hw_fmc_dataw2snml_t;

/*!
 * @name Constants and macros for entire FMC_DATAW2SnML register
 */
/*@{*/
#define HW_FMC_DATAW2SnML_COUNT (4U)

#define HW_FMC_DATAW2SnML_ADDR(x, n) ((x) + 0x288U + (0x10U * (n)))

#define HW_FMC_DATAW2SnML(x, n)  (*(__IO hw_fmc_dataw2snml_t *) HW_FMC_DATAW2SnML_ADDR(x, n))
#define HW_FMC_DATAW2SnML_RD(x, n) (HW_FMC_DATAW2SnML(x, n).U)
#define HW_FMC_DATAW2SnML_WR(x, n, v) (HW_FMC_DATAW2SnML(x, n).U = (v))
#define HW_FMC_DATAW2SnML_SET(x, n, v) (HW_FMC_DATAW2SnML_WR(x, n, HW_FMC_DATAW2SnML_RD(x, n) |  (v)))
#define HW_FMC_DATAW2SnML_CLR(x, n, v) (HW_FMC_DATAW2SnML_WR(x, n, HW_FMC_DATAW2SnML_RD(x, n) & ~(v)))
#define HW_FMC_DATAW2SnML_TOG(x, n, v) (HW_FMC_DATAW2SnML_WR(x, n, HW_FMC_DATAW2SnML_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW2SnML bitfields
 */

/*!
 * @name Register FMC_DATAW2SnML, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW2SnML_data (0U)        /*!< Bit position for FMC_DATAW2SnML_data. */
#define BM_FMC_DATAW2SnML_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnML_data. */
#define BS_FMC_DATAW2SnML_data (32U)       /*!< Bit field size in bits for FMC_DATAW2SnML_data. */

/*! @brief Read current value of the FMC_DATAW2SnML_data field. */
#define BR_FMC_DATAW2SnML_data(x, n) (HW_FMC_DATAW2SnML(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW2SnML_data. */
#define BF_FMC_DATAW2SnML_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnML_data) & BM_FMC_DATAW2SnML_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW2SnML_data(x, n, v) (HW_FMC_DATAW2SnML_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW2SnLM - Cache Data Storage (lowermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW2SnLM - Cache Data Storage (lowermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * lowermost word (bits [31:0]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw2snlm
{
    uint32_t U;
    struct _hw_fmc_dataw2snlm_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
    } B;
} hw_fmc_dataw2snlm_t;

/*!
 * @name Constants and macros for entire FMC_DATAW2SnLM register
 */
/*@{*/
#define HW_FMC_DATAW2SnLM_COUNT (4U)

#define HW_FMC_DATAW2SnLM_ADDR(x, n) ((x) + 0x28CU + (0x10U * (n)))

#define HW_FMC_DATAW2SnLM(x, n)  (*(__IO hw_fmc_dataw2snlm_t *) HW_FMC_DATAW2SnLM_ADDR(x, n))
#define HW_FMC_DATAW2SnLM_RD(x, n) (HW_FMC_DATAW2SnLM(x, n).U)
#define HW_FMC_DATAW2SnLM_WR(x, n, v) (HW_FMC_DATAW2SnLM(x, n).U = (v))
#define HW_FMC_DATAW2SnLM_SET(x, n, v) (HW_FMC_DATAW2SnLM_WR(x, n, HW_FMC_DATAW2SnLM_RD(x, n) |  (v)))
#define HW_FMC_DATAW2SnLM_CLR(x, n, v) (HW_FMC_DATAW2SnLM_WR(x, n, HW_FMC_DATAW2SnLM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW2SnLM_TOG(x, n, v) (HW_FMC_DATAW2SnLM_WR(x, n, HW_FMC_DATAW2SnLM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW2SnLM bitfields
 */

/*!
 * @name Register FMC_DATAW2SnLM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW2SnLM_data (0U)        /*!< Bit position for FMC_DATAW2SnLM_data. */
#define BM_FMC_DATAW2SnLM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnLM_data. */
#define BS_FMC_DATAW2SnLM_data (32U)       /*!< Bit field size in bits for FMC_DATAW2SnLM_data. */

/*! @brief Read current value of the FMC_DATAW2SnLM_data field. */
#define BR_FMC_DATAW2SnLM_data(x, n) (HW_FMC_DATAW2SnLM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW2SnLM_data. */
#define BF_FMC_DATAW2SnLM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnLM_data) & BM_FMC_DATAW2SnLM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW2SnLM_data(x, n, v) (HW_FMC_DATAW2SnLM_WR(x, n, v))
/*@}*/

/*******************************************************************************
 * HW_FMC_DATAW3SnUM - Cache Data Storage (uppermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW3SnUM - Cache Data Storage (uppermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * uppermost word (bits [127:96]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw3snum
{
    uint32_t U;
    struct _hw_fmc_dataw3snum_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [127:96] of data entry */
    } B;
} hw_fmc_dataw3snum_t;

/*!
 * @name Constants and macros for entire FMC_DATAW3SnUM register
 */
/*@{*/
#define HW_FMC_DATAW3SnUM_COUNT (4U)

#define HW_FMC_DATAW3SnUM_ADDR(x, n) ((x) + 0x2C0U + (0x10U * (n)))

#define HW_FMC_DATAW3SnUM(x, n)  (*(__IO hw_fmc_dataw3snum_t *) HW_FMC_DATAW3SnUM_ADDR(x, n))
#define HW_FMC_DATAW3SnUM_RD(x, n) (HW_FMC_DATAW3SnUM(x, n).U)
#define HW_FMC_DATAW3SnUM_WR(x, n, v) (HW_FMC_DATAW3SnUM(x, n).U = (v))
#define HW_FMC_DATAW3SnUM_SET(x, n, v) (HW_FMC_DATAW3SnUM_WR(x, n, HW_FMC_DATAW3SnUM_RD(x, n) |  (v)))
#define HW_FMC_DATAW3SnUM_CLR(x, n, v) (HW_FMC_DATAW3SnUM_WR(x, n, HW_FMC_DATAW3SnUM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW3SnUM_TOG(x, n, v) (HW_FMC_DATAW3SnUM_WR(x, n, HW_FMC_DATAW3SnUM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW3SnUM bitfields
 */

/*!
 * @name Register FMC_DATAW3SnUM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW3SnUM_data (0U)        /*!< Bit position for FMC_DATAW3SnUM_data. */
#define BM_FMC_DATAW3SnUM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnUM_data. */
#define BS_FMC_DATAW3SnUM_data (32U)       /*!< Bit field size in bits for FMC_DATAW3SnUM_data. */

/*! @brief Read current value of the FMC_DATAW3SnUM_data field. */
#define BR_FMC_DATAW3SnUM_data(x, n) (HW_FMC_DATAW3SnUM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW3SnUM_data. */
#define BF_FMC_DATAW3SnUM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnUM_data) & BM_FMC_DATAW3SnUM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW3SnUM_data(x, n, v) (HW_FMC_DATAW3SnUM_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW3SnMU - Cache Data Storage (mid-upper word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW3SnMU - Cache Data Storage (mid-upper word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-upper word (bits [95:64]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw3snmu
{
    uint32_t U;
    struct _hw_fmc_dataw3snmu_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [95:64] of data entry */
    } B;
} hw_fmc_dataw3snmu_t;

/*!
 * @name Constants and macros for entire FMC_DATAW3SnMU register
 */
/*@{*/
#define HW_FMC_DATAW3SnMU_COUNT (4U)

#define HW_FMC_DATAW3SnMU_ADDR(x, n) ((x) + 0x2C4U + (0x10U * (n)))

#define HW_FMC_DATAW3SnMU(x, n)  (*(__IO hw_fmc_dataw3snmu_t *) HW_FMC_DATAW3SnMU_ADDR(x, n))
#define HW_FMC_DATAW3SnMU_RD(x, n) (HW_FMC_DATAW3SnMU(x, n).U)
#define HW_FMC_DATAW3SnMU_WR(x, n, v) (HW_FMC_DATAW3SnMU(x, n).U = (v))
#define HW_FMC_DATAW3SnMU_SET(x, n, v) (HW_FMC_DATAW3SnMU_WR(x, n, HW_FMC_DATAW3SnMU_RD(x, n) |  (v)))
#define HW_FMC_DATAW3SnMU_CLR(x, n, v) (HW_FMC_DATAW3SnMU_WR(x, n, HW_FMC_DATAW3SnMU_RD(x, n) & ~(v)))
#define HW_FMC_DATAW3SnMU_TOG(x, n, v) (HW_FMC_DATAW3SnMU_WR(x, n, HW_FMC_DATAW3SnMU_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW3SnMU bitfields
 */

/*!
 * @name Register FMC_DATAW3SnMU, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW3SnMU_data (0U)        /*!< Bit position for FMC_DATAW3SnMU_data. */
#define BM_FMC_DATAW3SnMU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnMU_data. */
#define BS_FMC_DATAW3SnMU_data (32U)       /*!< Bit field size in bits for FMC_DATAW3SnMU_data. */

/*! @brief Read current value of the FMC_DATAW3SnMU_data field. */
#define BR_FMC_DATAW3SnMU_data(x, n) (HW_FMC_DATAW3SnMU(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW3SnMU_data. */
#define BF_FMC_DATAW3SnMU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnMU_data) & BM_FMC_DATAW3SnMU_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW3SnMU_data(x, n, v) (HW_FMC_DATAW3SnMU_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW3SnML - Cache Data Storage (mid-lower word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW3SnML - Cache Data Storage (mid-lower word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * mid-lower word (bits [63:32]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw3snml
{
    uint32_t U;
    struct _hw_fmc_dataw3snml_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
    } B;
} hw_fmc_dataw3snml_t;

/*!
 * @name Constants and macros for entire FMC_DATAW3SnML register
 */
/*@{*/
#define HW_FMC_DATAW3SnML_COUNT (4U)

#define HW_FMC_DATAW3SnML_ADDR(x, n) ((x) + 0x2C8U + (0x10U * (n)))

#define HW_FMC_DATAW3SnML(x, n)  (*(__IO hw_fmc_dataw3snml_t *) HW_FMC_DATAW3SnML_ADDR(x, n))
#define HW_FMC_DATAW3SnML_RD(x, n) (HW_FMC_DATAW3SnML(x, n).U)
#define HW_FMC_DATAW3SnML_WR(x, n, v) (HW_FMC_DATAW3SnML(x, n).U = (v))
#define HW_FMC_DATAW3SnML_SET(x, n, v) (HW_FMC_DATAW3SnML_WR(x, n, HW_FMC_DATAW3SnML_RD(x, n) |  (v)))
#define HW_FMC_DATAW3SnML_CLR(x, n, v) (HW_FMC_DATAW3SnML_WR(x, n, HW_FMC_DATAW3SnML_RD(x, n) & ~(v)))
#define HW_FMC_DATAW3SnML_TOG(x, n, v) (HW_FMC_DATAW3SnML_WR(x, n, HW_FMC_DATAW3SnML_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW3SnML bitfields
 */

/*!
 * @name Register FMC_DATAW3SnML, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW3SnML_data (0U)        /*!< Bit position for FMC_DATAW3SnML_data. */
#define BM_FMC_DATAW3SnML_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnML_data. */
#define BS_FMC_DATAW3SnML_data (32U)       /*!< Bit field size in bits for FMC_DATAW3SnML_data. */

/*! @brief Read current value of the FMC_DATAW3SnML_data field. */
#define BR_FMC_DATAW3SnML_data(x, n) (HW_FMC_DATAW3SnML(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW3SnML_data. */
#define BF_FMC_DATAW3SnML_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnML_data) & BM_FMC_DATAW3SnML_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW3SnML_data(x, n, v) (HW_FMC_DATAW3SnML_WR(x, n, v))
/*@}*/
/*******************************************************************************
 * HW_FMC_DATAW3SnLM - Cache Data Storage (lowermost word)
 ******************************************************************************/

/*!
 * @brief HW_FMC_DATAW3SnLM - Cache Data Storage (lowermost word) (RW)
 *
 * Reset value: 0x00000000U
 *
 * The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4
 * sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM,
 * DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set,
 * and the final two letters identify the word: UM (uppermost), MU (mid-upper),
 * ML (mid-lower), and LM (lowermost). This section represents data for the
 * lowermost word (bits [31:0]) of all 4 sets (n=0-3) in way 0.
 */
typedef union _hw_fmc_dataw3snlm
{
    uint32_t U;
    struct _hw_fmc_dataw3snlm_bitfields
    {
        uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
    } B;
} hw_fmc_dataw3snlm_t;

/*!
 * @name Constants and macros for entire FMC_DATAW3SnLM register
 */
/*@{*/
#define HW_FMC_DATAW3SnLM_COUNT (4U)

#define HW_FMC_DATAW3SnLM_ADDR(x, n) ((x) + 0x2CCU + (0x10U * (n)))

#define HW_FMC_DATAW3SnLM(x, n)  (*(__IO hw_fmc_dataw3snlm_t *) HW_FMC_DATAW3SnLM_ADDR(x, n))
#define HW_FMC_DATAW3SnLM_RD(x, n) (HW_FMC_DATAW3SnLM(x, n).U)
#define HW_FMC_DATAW3SnLM_WR(x, n, v) (HW_FMC_DATAW3SnLM(x, n).U = (v))
#define HW_FMC_DATAW3SnLM_SET(x, n, v) (HW_FMC_DATAW3SnLM_WR(x, n, HW_FMC_DATAW3SnLM_RD(x, n) |  (v)))
#define HW_FMC_DATAW3SnLM_CLR(x, n, v) (HW_FMC_DATAW3SnLM_WR(x, n, HW_FMC_DATAW3SnLM_RD(x, n) & ~(v)))
#define HW_FMC_DATAW3SnLM_TOG(x, n, v) (HW_FMC_DATAW3SnLM_WR(x, n, HW_FMC_DATAW3SnLM_RD(x, n) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual FMC_DATAW3SnLM bitfields
 */

/*!
 * @name Register FMC_DATAW3SnLM, field data[31:0] (RW)
 */
/*@{*/
#define BP_FMC_DATAW3SnLM_data (0U)        /*!< Bit position for FMC_DATAW3SnLM_data. */
#define BM_FMC_DATAW3SnLM_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnLM_data. */
#define BS_FMC_DATAW3SnLM_data (32U)       /*!< Bit field size in bits for FMC_DATAW3SnLM_data. */

/*! @brief Read current value of the FMC_DATAW3SnLM_data field. */
#define BR_FMC_DATAW3SnLM_data(x, n) (HW_FMC_DATAW3SnLM(x, n).U)

/*! @brief Format value for bitfield FMC_DATAW3SnLM_data. */
#define BF_FMC_DATAW3SnLM_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnLM_data) & BM_FMC_DATAW3SnLM_data)

/*! @brief Set the data field to a new value. */
#define BW_FMC_DATAW3SnLM_data(x, n, v) (HW_FMC_DATAW3SnLM_WR(x, n, v))
/*@}*/

/*******************************************************************************
 * hw_fmc_t - module struct
 ******************************************************************************/
/*!
 * @brief All FMC module registers.
 */
#pragma pack(1)
typedef struct _hw_fmc
{
    __IO hw_fmc_pfapr_t PFAPR;             /*!< [0x0] Flash Access Protection Register */
    __IO hw_fmc_pfb01cr_t PFB01CR;         /*!< [0x4] Flash Bank 0-1 Control Register */
    __IO hw_fmc_pfb23cr_t PFB23CR;         /*!< [0x8] Flash Bank 2-3 Control Register */
    uint8_t _reserved0[244];
    __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4];  /*!< [0x100] Cache Tag Storage */
    __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4];  /*!< [0x110] Cache Tag Storage */
    __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4];  /*!< [0x120] Cache Tag Storage */
    __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4];  /*!< [0x130] Cache Tag Storage */
    uint8_t _reserved1[192];
    struct {
        __IO hw_fmc_dataw0snum_t DATAW0SnUM; /*!< [0x200] Cache Data Storage (uppermost word) */
        __IO hw_fmc_dataw0snmu_t DATAW0SnMU; /*!< [0x204] Cache Data Storage (mid-upper word) */
        __IO hw_fmc_dataw0snml_t DATAW0SnML; /*!< [0x208] Cache Data Storage (mid-lower word) */
        __IO hw_fmc_dataw0snlm_t DATAW0SnLM; /*!< [0x20C] Cache Data Storage (lowermost word) */
    } DATAW0Sn[4];
    struct {
        __IO hw_fmc_dataw1snum_t DATAW1SnUM; /*!< [0x240] Cache Data Storage (uppermost word) */
        __IO hw_fmc_dataw1snmu_t DATAW1SnMU; /*!< [0x244] Cache Data Storage (mid-upper word) */
        __IO hw_fmc_dataw1snml_t DATAW1SnML; /*!< [0x248] Cache Data Storage (mid-lower word) */
        __IO hw_fmc_dataw1snlm_t DATAW1SnLM; /*!< [0x24C] Cache Data Storage (lowermost word) */
    } DATAW1Sn[4];
    struct {
        __IO hw_fmc_dataw2snum_t DATAW2SnUM; /*!< [0x280] Cache Data Storage (uppermost word) */
        __IO hw_fmc_dataw2snmu_t DATAW2SnMU; /*!< [0x284] Cache Data Storage (mid-upper word) */
        __IO hw_fmc_dataw2snml_t DATAW2SnML; /*!< [0x288] Cache Data Storage (mid-lower word) */
        __IO hw_fmc_dataw2snlm_t DATAW2SnLM; /*!< [0x28C] Cache Data Storage (lowermost word) */
    } DATAW2Sn[4];
    struct {
        __IO hw_fmc_dataw3snum_t DATAW3SnUM; /*!< [0x2C0] Cache Data Storage (uppermost word) */
        __IO hw_fmc_dataw3snmu_t DATAW3SnMU; /*!< [0x2C4] Cache Data Storage (mid-upper word) */
        __IO hw_fmc_dataw3snml_t DATAW3SnML; /*!< [0x2C8] Cache Data Storage (mid-lower word) */
        __IO hw_fmc_dataw3snlm_t DATAW3SnLM; /*!< [0x2CC] Cache Data Storage (lowermost word) */
    } DATAW3Sn[4];
} hw_fmc_t;
#pragma pack()

/*! @brief Macro to access all FMC registers. */
/*! @param x FMC module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 *     use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */
#define HW_FMC(x)      (*(hw_fmc_t *)(x))

#endif /* __HW_FMC_REGISTERS_H__ */
/* v33/140401/2.1.0 */
/* EOF */
